Semiconductor device and manufacturing method for the same

ABSTRACT

An N −  type epitaxial layer is formed on a P −  type silicon substrate. Trenches are created so as to penetrate N −  type epitaxial layer and so as to reach to a predetermined depth of P −  type silicon substrate. Thermal oxide films are formed on the sidewalls of trenches. Buried polysilicon films are formed so as to fill in trenches. Thermal oxide films are formed having an approximately constant film thickness ranging from the bottoms to the edges of the openings of trenches so as not to give stress to N −  type epitaxial layers. Thereby, a semiconductor device wherein a leak current is prevented can be gained.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and to amanufacturing method for the same, in particular, to a semiconductordevice having a trench for isolation and to a manufacturing method forthe same.

[0003] 2. Description of the Background Art

[0004] A variety of isolation structures for electrically insolatingelements from each other are utilized at the time when a plurality ofpredetermined elements, such as bipolar transistors, registers orcapacitors, are mounted in a semiconductor integrated circuit(hereinafter referred to as IC). The isolation structure that is mostwidely utilized is an isolation structure based on a PN junction.

[0005] In this isolation structure a PN junction is formed between aregion wherein elements are formed (element formation region) and anisolation region of which the conductive type is opposite to that of theelement formation region. Then, adjoining element formation regions areelectrically isolated from each other by applying a reverse bias to thisPN junction.

[0006] In a bipolar IC, an N⁻ type epitaxial layer is allowed to grow ona P⁻ type semiconductor substrate. In this case, it is necessary todefuse a P type diffusion layer in the depth direction by the filmthickness of the N⁻ type epitaxial layer in order to form an isolationregion. At this time, the P type diffusion layer spreads in the lateraldirection to approximately the same degree as the film thickness of theN⁻ type epitaxial layer.

[0007] Therefore, an extra distance between an element formation regionand an isolation region must be secured by taking the amount of spreadin the lateral direction of the above diffusion layer intoconsideration. In particular, since it is necessary to make the N⁻ typeepitaxial layer thick in a transistor of a high withstand voltage, theisolation region further spreads in the lateral direction so that thearea of the semiconductor device that includes the element formationregion and the isolation region becomes great.

[0008] In order to overcome this defect, a trench isolation structurehas been implemented in recent years. In a trench isolation structure adeep trench is created to reach to a predetermined depth in the P⁻ typesemiconductor substrate by penetrating the N⁻ type epitaxial layer andan insulator is filled in into this trench. Accordingly, a trenchisolation structure does not have spread in the lateral direction,unlike in the case of an isolation structure based on a PN junction, anda trench isolation region is formed so as to approximately attainpredetermined dimensions so that the density of integration of asemiconductor device can be greatly increased.

[0009] In the following, a manufacturing method for a bipolar IC of atrench isolation structure that has an NPN type bipolar transistor isdescribed as a conventional manufacturing method for a semiconductordevice.

[0010] First, as shown in FIG. 60, an N⁺ type buried layer 102 is formedon a P type silicon substrate 101. Next, an N⁻ type epitaxial layer isformed in accordance with an epitaxial growth method. Trenches 106 a and106 b are created by carrying out predetermined photomechanical, andother, processes so as to penetrate the N⁻ type epitaxial layer and soas to reach to a predetermined depth in P type silicon substrate 101.Thereby, N⁻ type epitaxial layer 103 is divided into three regions, N⁻type epitaxial layers 103 a to 103 c.

[0011] Next, reaction products produced during etching at the time ofthe creation of trenches 106 a and 106 b are removed by carrying outpredetermined wet etching or cleaning processes. After that, a thermaloxide film (not shown), which becomes a sacrificial oxide film, isformed on the surface of trenches 106 a and 106 b.

[0012] Next, boron is implanted through this thermal oxide film at anacceleration voltage of 50 KeV with the dosage amount of 1×10¹⁴/cm² and,thereby, channel cut layers 108 a and 108 b are formed in regions of P⁻type silicon substrate 101 located at the bottom of trenches 106 a and106 b. After that, the thermal oxide film is removed through wet etchingand a thermal oxide film 109 is formed.

[0013] Next, as shown in FIG. 61, a polysilicon film 110 is formed onthermal oxide film 109 so as to fill in trenches 106 a and 106 b. Next,as shown in FIG. 62, buried polysilicon films 110 a and 110 b are formedby carrying out etching on the entire surface of polysilicon film 110 soas to leave polysilicon film 110 only within trenches 106 a and 106 b.

[0014] Next, as shown in FIG. 63, thermal oxide film 109 is allowed toremain only within trenches 106 a and 106 b by carrying out wet etchingso as to remove thermal oxide film 109 located on N⁻ type epitaxiallayers 103 a to 103 c. At this time, etching is also carried out onportions of thermal oxide film 109 located on the sidewalls in thevicinity of the edges of the openings of trenches 106 a and 106 b sothat recesses 111 a to 111 d are created along the sidewalls in thevicinity of the edges of the openings of trenches 106 a and 106 b.

[0015] Next, as shown in FIG. 64, a thermal oxide film 112 is formed onN⁻ type epitaxial layers 103 a to 103 c by applying a thermal oxidationprocess. Through this thermal oxidation process, the exposed surface ofburied polysilicon films 110 a and 110 b is also oxidized.

[0016] Accordingly, the surface of buried polysilicon films 110 a and110 b and N⁻ type epitaxial layers 103 a to 103 c, which are exposed inrecesses 111 a to 111 d, is also oxidized in the upper portions oftrenches 106 a and 106 b so that thick oxide films 109 a and 109 b areformed between buried polysilicon films 110 a, 110 b and N⁻ typeepitaxial layers 103 a to 103 c. Then, recesses 113 a to 113 d arecreated through the formation of thick oxide films 109 a and 109 b inthermal oxide film 112.

[0017] Next, as shown in FIG. 65, a collector lead-out layer 114 and abase lead-out layer 116 are, respectively, formed by means of apredetermined gas diffusion method. After that, thermal oxide film 112is removed and a new thermal oxide film 118 is formed. At this time, inthe case that etching of thermal oxide film 112 is carried out to anexcessive degree, recesses 113 a to 113 d are spread so that thickerthermal oxide film is formed on the portions of these recesses 113 a to113 d during thermal oxidation at the time of the formation of thermaloxide film 118.

[0018] Next, as shown in FIG. 66, a base diffusion layer 121 is formedby implanting boron ions, for example, into N⁻ type epitaxial layer 103b by means of an ion implantation method. At this time, a thermaloxidation process is also carried out when boron is diffused by means ofa thermal treatment (boron drive) and, thereby, the film thickness ofthermal oxide film 118 becomes greater.

[0019] Next, as shown in FIG. 67, an emitter diffusion layer 124 a and acollector diffusion layer 124 b are formed on N⁻ type epitaxial layer103 b. After that, metal silicide layers 127 a to 127 c, such as ofTiSi₂, barrier metal layers 128 a to 128 c, such as of TiN, and metalwires 129 a to 129 c, such as of AlCu, are, for example, formed.Thereby, an NPN transistor T is completed.

[0020] In the above-described conventional manufacturing method for asemiconductor device, however, it is found that the following problemsexist. That is to say, when predetermined voltages are applied,respectively, between N⁻ type epitaxial layer 103 a and N⁻ typeepitaxial layer 103 b or between epitaxial layer 103 b and N⁻ typeepitaxial layer 103 c, it is found that a comparatively large amount ofleak current occurs with the result that the elements formed in therespective N⁻ type epitaxial layers 103 a to 103 c can not besufficiently electrically isolated from each other.

SUMMARY OF THE INVENTION

[0021] The present invention is provided to solve the above-describedproblems and one purpose thereof is to provide a semiconductor devicewherein a leak current is prevented while another purpose thereof is toprovide a manufacturing method for such a semiconductor device.

[0022] The inventors repeated experiments to search for the causes ofthe leak current and found that the leak current can be greatly reducedby preventing recesses 113 a to 113 d created in the sidewall portionsin the vicinity of the edges of the openings of trenches 106 a and 106 bfor isolation from becoming large and by preventing the film thicknessof the thermal oxide film in those portions from becoming great.

[0023] Then, the inventors determined that the leak current is caused bylocal stress given to N⁻ type epitaxial layers 113 a to 113 c due tocomparatively thick silicon oxide films formed in recesses 113 a to 113d located along the sidewalls in the vicinity of the edges of theopenings of the trenches.

[0024] In the following, a semiconductor device according to theinvention and the configuration of a manufacturing method for the sameare described.

[0025] The semiconductor device according to one aspect of the presentinvention is provided with a semiconductor substrate of a firstconductive type having a main surface, a layer of second conductivetype, a trench portion, an insulating film and a buried semiconductorregion. The layer of the second conductive type is formed on the mainsurface of the semiconductor substrate of the first conductive type. Thetrench portion is created so as to penetrate the layer of the secondconductive type and to reach to a region of the semiconductor substrateand separates the layer of the second conductive type into one elementformation region and another element formation region. The insulatingfilm is formed on the sidewalls of the trench portion. The buriedsemiconductor region is formed on the insulating film so as to fill inthe trench portion. Then, the insulating film, having an approximatelyuniform film thickness, is formed from the bottom of the trench portionover to the edges of the opening so as not to give any stress to thelayer of the second conductive type.

[0026] Because of this structure, the insulating film, having anapproximately uniform film thickness, formed on the sidewalls of thetrench portion is formed from the bottom of the trench portion over tothe edges of the opening so as not to give any stress to the layer ofthe second conductive type and, thereby, the layer of the secondconductive type is prevented from being affected by stress. As a result,the leak current that occurs between one element formation region andanother element formation region can be reduced so that the elementsformed in the respective element formation regions can be electricallyisolated.

[0027] A manufacturing method for a semiconductor device according toanother aspect of the present invention is provided with the followingsteps. A layer of a second conductive type is formed on a main surfaceof a semiconductor substrate of a first conductive type. A trenchportion is created so as to divide the layer of the second conductivetype into one element formation region and another element formationregion. A first insulating film is formed on the layer of the secondconductive type that includes the sidewalls exposed within the trenchportion. A semiconductor film is formed on the first insulating film soas to fill in the trench portion. A buried semiconductor region isformed so that the semiconductor film remains within the trench portion.A thermal treatment is carried out on the first insulating film that islocated on the top surface of the layer of second conductive type and,thereby, a second insulating film that is thicker than the firstinsulating film is formed.

[0028] Because of this manufacturing method, a thermal treatment iscarried out on the first insulating film that is formed on the layer ofthe second conductive type that includes the sidewalls exposed withinthe trench portion and, thereby, no recesses are formed along thesidewalls of the edges of the openings of the trench portion so that aportion of the first insulating film that is located in this portion canbe prevented from becoming thicker through the thermal treatment incomparison with the conventional manufacturing method wherein the secondinsulating film is formed after removing the first insulating film thatis located on the layer of the second conductive type. Thereby, aninsulating film having an approximately uniform thickness is formed fromthe bottom of the trench portion over to the edges of the opening sothat a stress is prevented from affecting the layer of the secondconductive type. As a result, the leak current that occurs between oneelement formation region and another element formation region is reducedand, thereby, a semiconductor device is gained that can electricallyisolate the elements that are formed in the respective element formationregions without fail.

[0029] Another manufacturing method for a semiconductor device accordingto another aspect of the present invention is provided with thefollowing steps. A layer of a second conductive type is formed on a mainsurface of a semiconductor substrate of a first conductive type. Atrench portion is created for dividing the layer of the secondconductive type into one element formation region and another elementformation region. An oxidation blocking film is formed on sidewallsexposed within the trench portion. A semiconductor film is formed on theoxidation blocking film so as to fill in the trench portion. A buriedsemiconductor region is formed so that the semiconductor film remainswithin the trench portion. An insulating film is formed on the layer ofthe second conductive type by carrying out a thermal treatment.

[0030] Because of this manufacturing method, an oxidation blocking filmis formed on the sidewalls exposed within the trench portion and,thereby, the portion of the trench portion in the upper portion of thesidewalls is prevented from being oxidized at the time of the thermaltreatment so that the layer of the second conductive type is preventedfrom being affected by stress. As a result, a semiconductor device isgained wherein the leak current that occurs between one elementformation region and another element formation region can be reduced sothat the elements formed in the respective element formation regions canbe electrically isolated without fail.

[0031] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment1 of the present invention;

[0033]FIG. 2 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 1 according to Embodiment 1;

[0034]FIG. 3 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 2 according to Embodiment 1;

[0035]FIG. 4 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 3 according to Embodiment 1;

[0036]FIG. 5 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 4 according to Embodiment 1;

[0037]FIG. 6 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 5 according to Embodiment 1;

[0038]FIG. 7 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 6 according to Embodiment 1;

[0039]FIG. 8 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 7 according to Embodiment 1;

[0040]FIG. 9 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 8 according to Embodiment 1;

[0041]FIG. 10 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 9 according to Embodiment 1;

[0042]FIG. 11 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 10 according to Embodiment 1;

[0043]FIG. 12 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 11 according to Embodiment 1;

[0044]FIG. 13 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 12 according to Embodiment 1;

[0045]FIG. 14 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 13 according to Embodiment 1;

[0046]FIG. 15 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 14 according to Embodiment 1;

[0047]FIG. 16 is a schematic diagram showing a path of a leak current inEmbodiment 1;

[0048]FIG. 17 is a graph showing the relationship between the voltageapplied between the epitaxial layers and the leak current in Embodiment1;

[0049]FIG. 18 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment2 of the present invention;

[0050]FIG. 19 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 18 according to Embodiment 2;

[0051]FIG. 20 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 19 according to Embodiment 2;

[0052]FIG. 21 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 20 according to Embodiment 2;

[0053]FIG. 22 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 21 according to Embodiment 2;

[0054]FIG. 23 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 22 according to Embodiment 2;

[0055]FIG. 24 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 23 according to Embodiment 2;

[0056]FIG. 25 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 24 according to Embodiment 2;

[0057]FIG. 26 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment3 of the present invention;

[0058]FIG. 27 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 26 according to Embodiment 3;

[0059]FIG. 28 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 27 according to Embodiment 3;

[0060]FIG. 29 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 28 according to Embodiment 3;

[0061]FIG. 30 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment4 of the present invention;

[0062]FIG. 31 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 30 according to Embodiment 4;

[0063]FIG. 32 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 31 according to Embodiment 4;

[0064]FIG. 33 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 32 according to Embodiment 4;

[0065]FIG. 34 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment5 of the present invention;

[0066]FIG. 35 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 34 according to Embodiment 5;

[0067]FIG. 36 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 35 according to Embodiment 5;

[0068]FIG. 37 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 36 according to Embodiment 5;

[0069]FIG. 38 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment6 of the present invention;

[0070]FIG. 39 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 38 according to Embodiment 6;

[0071]FIG. 40 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 39 according to Embodiment 6;

[0072]FIG. 41 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 40 according to Embodiment 6;

[0073]FIG. 42 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 41 according to Embodiment 6;

[0074]FIG. 43 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 42 according to Embodiment 6;

[0075]FIG. 44 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 43 according to Embodiment 6;

[0076]FIG. 45 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 44 according to Embodiment 6;

[0077]FIG. 46 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 45 according to Embodiment 6;

[0078]FIG. 47 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to Embodiment7 of the present invention;

[0079]FIG. 48 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 47 according to Embodiment 7;

[0080]FIG. 49 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 48 according to Embodiment 7;

[0081]FIG. 50 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 49 according to Embodiment 7;

[0082]FIG. 51 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 50 according to Embodiment 7;

[0083]FIG. 52 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 51 according to Embodiment 7;

[0084]FIG. 53 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 52 according to Embodiment 7;

[0085]FIG. 54 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 53 according to Embodiment 7;

[0086]FIG. 55 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 54 according to Embodiment 7;

[0087]FIG. 56 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 55 according to Embodiment 7;

[0088]FIG. 57 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 56 according to Embodiment 7;

[0089]FIG. 58 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 57 according to Embodiment 7;

[0090]FIG. 59 is a cross sectional view including a PN isolation typetransistor as a comparison for describing the effects of thesemiconductor device shown in FIG. 58 according to Embodiment 7;

[0091]FIG. 60 is a cross sectional view showing one step of amanufacturing method for a semiconductor device according to a priorart;

[0092]FIG. 61 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 60;

[0093]FIG. 62 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 61;

[0094]FIG. 63 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 62;

[0095]FIG. 64 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 63;

[0096]FIG. 65 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 64;

[0097]FIG. 66 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 65; and

[0098]FIG. 67 is a cross sectional view showing a step that is carriedout after the step shown in FIG. 66.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0099] Embodiment 1

[0100] A manufacturing method for a semiconductor device according toEmbodiment 1 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, as shown in FIG. 1, an N⁺ type buried layer 2 is formed on a P⁻type silicon substrate 1. N⁺ type buried layer 2 becomes the lowresistance portion of the collector in an NPN transistor. The depth ofthis N⁺ type buried layer 2 is approximately 5 μm.

[0101] Next, an N⁻ type epitaxial layer 3 is formed in accordance withan epitaxial growth method. N⁺ type buried layer 2 diffuses upward toexceed P type silicon substrate 1 during the epitaxial growth. The filmthickness of this N⁻ type epitaxial layer 3 is approximately 6 μm. Athermal oxide film 4, of which the film thickness is approximately 0.5μm, is formed on this N⁻ type epitaxial layer 3 in accordance with athermal oxidation method. A silicon oxide film 5, of which the filmthickness is approximately 1 μm, is formed on this thermal oxide film 4in accordance with a CVD (chemical vapor deposition) method.

[0102] After that, a photoresist (not shown) is applied and patterningis carried out so that openings are created in the photoresist locatedabove the region wherein trenches for isolation are created. Next,reactive anisotropic etching is carried out by using the photoresist asa mask and, thereby, portions of silicon oxide film 5 and thermal oxidefilm 4 located above the regions in which the trenches are created areremoved so that silicon oxide films 5 a to 5 c and 4 a to 4 c, whichbecome a mask, are formed (referring to FIG. 2). After that, thephotoresist is removed.

[0103] Next, as shown in FIG. 2, reactive anisotropic etching is carriedout using silicon oxide films 5 a to 5 c and 4 a to 4 c as a mask and,thereby, trenches 6 a and 6 b are created so as to penetrate N⁻ typeepitaxial layer 3 and so as to reach to a predetermined depth in P⁻ typesilicon substrate 1. The depth of these trenches 6 a and 6 b isapproximately 15 μm.

[0104] These trenches 6 a and 6 b become isolation regions so as todivide N⁻ type epitaxial layer 3 into three N⁻ type epitaxial layers 3 ato 3 c. Here, the sidewall portions of the openings in silicon oxidefilms 5 a to 5 c and 4 a to 4 c acting as a mask have a tapered formbecause etching is gradually carried out on the surface of thesesidewalls through silicon etching at the time of the creation oftrenches 6 a and 6 b. After that, wet etching and a cleaning process arecarried out and, thereby, reaction products that have been producedthrough silicon etching at the time of the creation of trenches 6 a and6 b are removed.

[0105] Next, as shown in FIG. 3, thermal oxide films 7 a and 7 b, ofwhich the film thickness is approximately 50 nm, are formed inaccordance with a thermal oxidation method. These thermal oxide films 7a and 7 b are so-called sacrificial oxide films. The silicon surfaces ofthe sidewalls and of the bottoms of trenches 6 a and 6 b that havereceived damage through silicon etching are oxidized so that theseoxidized portions are subsequently removed.

[0106] Next, as shown in FIG. 4, boron is implanted at the accelerationvoltage of 50 KeV in the dosage amount of 1×10¹⁴/cm² using silicon oxidefilms 5 a to 5 c and 4 a to 4 c as a mask and, thereby, channel cutlayers 8 a and 8 b are formed in the regions of P⁻ type siliconsubstrate 1 located at the bottoms of trenches 6 a and 6 b.

[0107] These channel cut layers 8 a and 8 b are formed in order toprevent the formation of a leak current path between N⁻ type epitaxiallayer 3 a and N⁻ type epitaxial layer 3 b or between N⁻ type epitaxiallayer 3 b and N⁻ type epitaxial layer 3 c. Next, wet etching is carriedout so as to remove silicon oxide films 5 a to 5 c, 4 a to 4 c, 7 a and7 b. After that, a thermal oxide film 9, of which the film thickness isapproximately 0.1 μm, is formed in accordance with a thermal oxidationmethod.

[0108] Next, as shown in FIG. 5, a polysilicon film 10, of which thefilm thickness is approximately 2 μm, is formed on thermal oxide film 9so as to fill in trenches 6 a and 6 b. Next, as shown in FIG. 6, etchingis carried out on the entire surface of polysilicon film 10 and,thereby, buried polysilicon films 10 a and 10 b are formed so that thepolysilicon films remain within trenches 6 a and 6 b.

[0109] Etching is carried out on the entire surface of polysilicon film10 and, thereby, etching is analog carried out on exposed thermal oxidefilm 9 so that the film thickness (thickness of remaining film) ofthermal oxide film 9, which has remained on N⁻ type epitaxial layers 3 ato 3 c, is approximately 90 nm. However, the top surfaces of N⁻ typeepitaxial layers 3 a to 3 c are not exposed.

[0110] Here, in the case that an impurity of a predetermined conductivetype is added to a polysilicon film, the amount (film thickness) of thepolysilicon film that is oxidized in a subsequent oxidation processincreases in comparison with the case when the impurity is not added tothe polysilicon film. Therefore, as described below, it is preferable toutilize a polysilicon film to which an impurity is not added aspolysilicon film 10 in order to reduce the leak current by preventingthe film thickness of the thermal oxide film from increasing in theupper portions of the sidewalls of trenches 6 a and 6 b.

[0111] Next, as shown in FIG. 7, a thermal oxide film 31 is formed bycarrying out a thermal oxidation process so as to increase the thicknessof thermal oxide film 9. This thermal oxide film 31 is formed so thatthe film thickness thereof becomes approximately 0.6 μm. This thermaloxide film 31 corresponds to thermal oxide film 112 according to theprior art.

[0112] Next, as shown in FIG. 8, phosphorous is introduced to acollector lead-out portion 15 in accordance with a gas diffusion methodso as to form a collector lead-out layer 14. A thermal oxidation processis also carried out at the time when the phosphorus is diffused(phosphorus drive) in accordance with a thermal treatment and, thereby,a thermal oxide film, of which the film thickness is approximately 0.4μm, is formed in collector lead-out portion 15.

[0113] Here, the phosphorus gas diffusion is implemented by carrying outa thermal treatment on the silicon substrate (wafer) for, for example,10 to 30 minutes while a small amount (up to 1 l/min) of PH₃ gas, asmall amount (up to 1 l/min) of O₂ gas and a large amount (up to 50l/min) of N₂ gas are made to flow in a diffusion furnace at atemperature of, for example, approximately 1000° C.

[0114] Next, as shown in FIG. 9, boron is introduced into a baselead-out portion 13 in accordance with a gas diffusion method so as toform a base lead-out layer 16. A thermal oxidation process is alsocarried out at the time when the boron is diffused (boron drive) bymeans of a thermal treatment and, thereby, a thermal oxide film isformed in a base lead-out portion 17.

[0115] Here, the boron gas diffusion is implemented by carrying out athermal treatment on the silicon substrate (wafer) for, for example, 10to 30 minutes while a small amount (up to 1 l/min) of B₂H₆ gas, a smallamount (up to 1 l/min) of O₂ gas and a large amount (up to 50 l/min) ofN₂ gas are made to flow in a diffusion furnace at a temperature of, forexample, approximately 1000° C.

[0116] Next, thermal oxide film 31 is removed by carrying out etching onthe entire surface of thermal oxide film 31. At this time, it isnecessary to be careful not to allow recesses 32 a to 32 b in the upperportions of the sidewalls of trenches 6 a and 6 b to become large bylimiting etching of thermal oxide film 31 to the least required amount.Therefore, it is necessary to adopt etching conditions wherein, in thecase that the portions of thermal oxide film 31 located above a basediffusion layer 21 formed in a subsequent process can be removed,remaining portions of thermal oxide film 31 are allowed to exist in theother regions.

[0117] Concretely, the film thickness of thermal oxide film 31 locatedabove base diffusion layer 21 is measured in advance before etching andthe period of time of etching required to remove thermal oxide film 31is found from the film thickness thereof and the etching rate and, then,etching is carried out so that no portions of thermal oxide film 31located above this base diffusion layer 21 remain and, thereby, overetching can be reduced to the minimum.

[0118] After that, as shown in FIG. 10, a thermal oxide film 33, ofwhich the film thickness is approximately 0.1 μm, is formed by carryingout a thermal oxidation process. Next, as shown in FIG. 11, apredetermined photoresist 19 is formed on thermal oxide film 33. Thisphotoresist 19 is used as a mask so as to implant boron and, thereby,boron ions are introduced into the surface of N⁻ type epitaxial layer 3b.

[0119] After that, photoresist 19 is removed and a base diffusion layer21 is formed, as shown in FIG. 12, by diffusing the boron (boron drive)by means of a thermal treatment. Next, as shown in FIG. 13, aphotoresist 22 is formed on thermal oxide film 33. This photoresist 22is used as a mask so as to carry out predetermined anisotropic etchingand, thereby, thermal oxide film 33 above the regions that become anemitter region and a collector region is removed so that openings 33 aand 33 b are, respectively, created.

[0120] Next, arsenic ions are introduced into the surface of N⁻ typeepitaxial layer 3 b by implanting arsenic ions 23. After that,photoresist 22 is removed. Then, an emitter diffusion layer 24 a and acollector contact layer 24 b are formed as shown in FIG. 14 by diffusingthe arsenic (arsenic drive) by means of a thermal treatment.

[0121] After that, a silicon oxide film 25 is formed on thermal oxidefilm 33 by means of a CVD method. Predetermined photomechanical processand etching are carried out on that silicon oxide film 25 and thermaloxide film 33 and, thereby, an emitter contact hole 26 a, a base contacthole 26 b and a collector contact hole 26 c are, respectively, created.

[0122] Next, as shown in FIG. 15, metal silicide layers 27 a to 27 c,such as of TiSi₂, barrier metal layers 28 a to 28 c, such as of TiN, andmetal wires 29 a to 29 c, such as of AlCu, are formed and, thereby, anNPN transistor T is completed.

[0123] In contrast to the conventional manufacturing method for asemiconductor device wherein thermal oxide film 109 located on N⁻ typeepitaxial layers 103 a to 103 c is removed through etching in the stepshown in FIG. 63, etching is not carried out at all on thermal oxidefilm 9 located on N⁻ type epitaxial layers 3 a to 3 c in the steps shownin FIGS. 6 and 7 according to the above-described manufacturing method.

[0124] Thereby, in the step shown in FIG. 6, recesses 111 a to 111 d, asshown in FIG. 63, are not created along the sidewalls in the vicinity ofthe edges of the openings of trench portions 6 a and 6 b. Therefore, atthe time of thermal oxidation processing carried out for forming thermaloxide film 31 in the next step shown in FIG. 7, the portions of thermaloxide films 109 a and 109 b located on the sidewalls in the vicinity ofthe openings of trenches 106 a and 106 b are prevented from becomingthicker due to the oxidation of the portions of N⁻ type epitaxial layers103 a to 103 c and the portions of buried polysilicon films 110 a and110 b that are exposed in recesses 111 a to 111 d, unlike in theconventional manufacturing method.

[0125] Accordingly, recesses 32 a to 32 d that are formed in thermaloxide film 31 located on the sidewalls in the vicinity of the edges ofthe openings of trenches 6 a and 6 b become small in comparison withthose in the conventional manufacturing method.

[0126] Then, according to this manufacturing method for a semiconductordevice, etching is further carried out on thermal oxide film 31 to therequired minimum amount so that the portion of thermal oxide film 31located above base diffusion layer 21 can be removed immediately afterthe step shown in FIG. 9 and, after that, a thermal treatment is carriedout for the formation of thermal oxide film 33 in the step shown in FIG.10.

[0127] Thereby, excessive etching is not carried out in recesses 32 a to32 d formed in thermal oxide film 31, so that recesses 32 a to 32 d areprevented from becoming large. Since recesses 32 a to 32 d are preventedfrom becoming large, recesses 32 a to 32 d created in thermal oxide film33 also become small.

[0128] Thus, according to the present manufacturing method for asemiconductor device, etching is not carried out at all on thermal oxidefilm 9 located on N⁻ type epitaxial layers 3 a to 3 c and, thereby,large recesses are prevented from being created along the sidewalls inthe vicinity of the edges of the openings of trenches 6 a and 6 b.

[0129] Thereby, the portions of thermal oxide film 9 a and 9 b locatedon the sidewalls in the vicinity of the edges of the openings areprevented from becoming thick at the time of the formation of thermaloxide film 31 so that recesses 32 a to 32 d that occur in the portionsof thermal oxide film 31 located on these sidewalls also become smaller.

[0130] Furthermore, since predetermined etching is carried out onthermal oxide film 31 to the required minimum amount, recesses 32 a to32 d are prevented from becoming large so that recesses 32 a to 32 dthat occur in subsequently formed thermal oxide film 33 also becomesmall.

[0131] Thereby, thermal oxide films 9 a and 9 b extending from thebottoms of trenches 6 a and 6 b over to the edges of the openings areformed so as to have a substantially uniform film thickness in thecompleted semiconductor device.

[0132] An evaluation of the leak current is carried out in thesemiconductor device formed in the above-described manner as well as inthe conventional semiconductor device. The result thereof is shown inFIGS. 16 and 17. FIG. 16 shows a path (arrow) of a leak current I_(CC)in the case that a voltage V_(CC) is applied between N⁻ type epitaxiallayer 3 a and N⁻ type epitaxial layer 3 b that are electrically isolatedby trench 6 a. In the conventional semiconductor device, as shown inFIG. 16, a component L of the leak current that flows through theportion of N⁻ type epitaxial layer 3 a located in the vicinity of theedges of the opening of trench 6 a is recognized.

[0133] In contrast to this, in the semiconductor device gained accordingto the present manufacturing method, the film thickness of the thermaloxide film located on the sidewalls in the vicinity of the edges of theopening of trench 6 a is prevented from becoming great, as shown in B ofFIG. 15. Therefore, the stress to N⁻ type epitaxial layer 3 a in thisportion is relieved.

[0134] As a result of this, it is found that component L of theabove-described leak current that flows through the N⁻ type epitaxiallayer in the vicinity of the edge of the opening is reduced and, asshown in FIG. 17, leak current I_(CC) is reduced in the presentsemiconductor device in comparison with the conventional semiconductordevice for the same applied voltage V_(CC).

[0135] In accordance with the above description, it is contemplated thatthermal oxide films 9 a and 9 b extending from the bottoms of trenches 6a and 6 b over to the edges of the openings are formed so as to have anapproximately constant film thickness so that stress is not given to N⁻type epitaxial layers 3 a to 3 c.

[0136] Embodiment 2

[0137] A manufacturing method for a semiconductor device according toEmbodiment 2 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, the steps up to the step shown in FIG. 18 are the same as thoseshown in FIGS. 1 to 6 described in Embodiment 1. In this step shown inFIG. 18, the film thickness of a thermal oxide film 9 is approximately90 nm.

[0138] Next, as shown in FIG. 19, a photoresist 41 is formed on thermaloxide film 9. This photoresist 41 is used as a mask for introducingphosphorous ions 42 into a collector lead-out portion 43. A collectorlead-out layer is formed by carrying out a thermal treatment in order todiffuse the phosphorous (phosphorous drive). Here, it is desirable tocarry out this thermal treatment for the phosphorous drive under thecondition wherein oxidation does not occur. Thereby, as shown in FIG.20, a collector lead-out layer 43 is formed.

[0139] Next, as shown in FIG. 21, a photoresist 44 is formed on thermaloxide film 9. This photoresist 44 is used as a mask for introducingboron ions 45 into a base lead-out portion 46. Base lead-out layer 46 isformed, as shown in FIG. 22, by carrying out a thermal treatment inorder to diffuse the boron (boron drive). Here, it is preferable tocarry out the thermal treatment for the boron drive under the conditionwherein oxidation does not occur.

[0140] Here, collector lead-out layer 43 and base lead-out layer 46 areformed by means of an ion implantation method because thermal oxide film9 is comparatively thin and thermal oxide film 9 can not be utilized asa diffusion mask in a gas diffusion method.

[0141] Next, as shown in FIG. 23, thermal oxide film 9 is made thickerby carrying out a thermal oxidation process and, thereby, a thermaloxide film 48 is formed. The thickness of this thermal oxide film 48 isapproximately 0.1 μm. This step, shown in FIG. 23, corresponds to thestep shown in FIG. 10 described in Embodiment 1.

[0142] After that, the step shown in FIG. 11 and the step shown in FIG.12 described in Embodiment 1 are carried out so as to gain the structureshown in FIG. 24. Furthermore, after that, the same steps as those fromthe step shown in FIG. 13 to the step shown in FIG. 15 described inEmbodiment 1 are followed so as to complete an NPN transistor T, asshown in FIG. 25.

[0143] According to the above described manufacturing method for asemiconductor device, etching is not carried out at all on thermal oxidefilm 9 located on N⁻ type epitaxial layers 3 a to 3 c as described inEmbodiment 1 and, thereby, the portions of thermal oxide film 9 a and 9b located on the sidewalls in the vicinity of the edges of the openingsof trenches 6 a and 6 b are prevented from becoming thicker at the timewhen thermal oxide film 31 is formed.

[0144] Furthermore, according to the above described manufacturingmethod, etching that corresponds to the etching of thermal oxide film31, which is carried out between the step shown in FIG. 9 and the stepshown in FIG. 10 described in Embodiment 1, is not carried out and,therefore, a further thermal oxidation process is carried out on thermaloxide film 48, in the step shown in FIG. 24, so that thermal oxide film48 becomes thicker during formation.

[0145] Thereby, recesses 47 a to 47 d that occur in thermal oxide film48 located in on the sidewalls in the vicinity of the edges of theopenings of trenches 6 a and 6 b become smaller in comparison with thecase of Embodiment 1 so that the film thickness of thermal oxide film 48in these portions can be prevented from becoming greater.

[0146] As a result, as is described in Embodiment 1, the leak currentbetween N⁻ type epitaxial layers 3 a to 3 c is reduced so that theelements, such as transistors, formed in each N⁻ type epitaxial layer 3a to 3 c can be electrically isolated from each other without fail.

[0147] Embodiment 3

[0148] A manufacturing method for a semiconductor device according toEmbodiment 3 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, the steps up to the step shown in FIG. 26 are the same as thoseshown in FIGS. 1 to 5 described in Embodiment 1.

[0149] Next, as shown in FIG. 27, etching is carried out on the entiresurface of a polysilicon film 10 to such a degree that a slight amountof polysilicon film 10 remains on thermal oxide film 9. The filmthickness of remaining polysilicon film 10 at this time may be 50 nm, orless. Next, as shown in FIG. 28, a thermal oxide film 51 is formed bycarrying out a thermal oxidation process under the condition whereinpolysilicon film 10 remains. The thickness of thermal oxide film 51 isapproximately 0.6 μm.

[0150] Here, as described in Embodiment 1, it is preferable thatimpurities are not added to buried polysilicon film 10 a or 10 b.

[0151] After that, the same steps as those from the step shown in FIG. 8to the step shown in FIG. 15 described in Embodiment 1 are followed and,thereby, an NPN transistor T is completed, as shown in FIG. 29.

[0152] According to the above described manufacturing method for asemiconductor device, the etching of the entire surface of polysiliconfilm 10 in the step shown in FIG. 27 is carried out to such a degreethat polysilicon film 10 remains on thermal oxide film 9. Then, athermal oxidation process is carried out under the condition whereinsuch a polysilicon film 10 remains in the step shown in FIG. 28 and,thereby, a thermal oxide film 51 is formed. Thereby, recesses 52 a to 52d that occur in thermal oxide film 51 become smaller.

[0153] Furthermore, predetermined etching is carried out on this thermaloxide film 51 to the required minimum amount in the same step as thestep shown in FIG. 9 described in Embodiment 1 and, after that, athermal oxidation process is carried out.

[0154] Thereby, recesses 13 a to 13 d that occur in the portions ofthermal oxide film 51 located on the sidewalls in the vicinity of theedges of the openings of trenches 6 a and 6 b are prevented frombecoming larger so that the film thickness of thermal oxide films 9 aand 9 b can be prevented from becoming greater in these portions.

[0155] As a result, the leak current between respective N⁻ typeepitaxial layers 3 a, 3 b and 3 c is extremely small so that theelements, such as transistors, formed in each of N⁻ type epitaxiallayers 3 a to 3 c can be sufficiently electrically isolated.

[0156] Embodiment 4

[0157] A manufacturing method for a semiconductor device according toEmbodiment 4 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, the steps up to the step shown in FIG. 30 are the same as thoseshown in FIGS. 1 to 5 described in Embodiment 1.

[0158] Next, as shown in FIG. 31, a CMP (chemical mechanical polishing)polishing process is carried out on polysilicon film 10. According tothis CMP polishing process, the top surface of buried polysilicon films10 a and 10 b and the surface of thermal oxide film 9 are positioned inapproximately the same plane. Next, as shown in FIG. 32, a thermal oxidefilm 61, of which the film thickness is approximately 0.6 μm, is formedby carrying out a thermal oxidation process.

[0159] At this time, as described in Embodiment 1, etching is notcarried out at all on thermal oxide film 9 located on N⁻ type epitaxiallayers 3 a to 3 c and, thereby, the portions of the thermal oxide films9 a and 9 b located on the sidewalls in the vicinity of the edges of theopenings of trenches 6 a and 6 b are prevented from becoming thick atthe time when thermal oxide film 31 is formed. Thereby, recesses 62 a to62 d that occur in thermal oxide film 61 become comparatively small.Here, as described in Embodiment 1, it is preferable that impurities notbe added to buried polysilicon film 10 a or lob.

[0160] After that, the same steps as those from the step shown in FIG. 8to the step shown in FIG. 15 described in Embodiment 1 are followed soas to complete an NPN transistor T, as shown in FIG. 33.

[0161] According to the above described manufacturing method for asemiconductor device, etching is not carried out at all on thermal oxidefilm 9 located on N⁻ type epitaxial layers 3 a to 3 c as described inEmbodiment 1 and, thereby, the portions of thermal oxide films 9 a and 9b located on the sidewalls in the vicinity of the edges of the openingsof trenches 6 a and 6 b are prevented from becoming thick at the timewhen thermal oxide film 61 is formed.

[0162] Furthermore, predetermined etching is carried out on this thermaloxide film 61 to the required minimum amount in a step similar to thestep shown in FIG. 9 described in Embodiment 1 and, after that, athermal oxidation process is carried out.

[0163] Thereby, recesses 62 a to 62 d that occur in the portions ofthermal oxide film 61 located on the sidewalls in the vicinity of theedges of the openings of trenches 6 a and 6 b are prevented frombecoming large so that the film thickness of thermal oxide films 9 a and9 b located on the sidewalls in the vicinity of the edges of theopenings of trenches 6 a and 6 b can be prevented from becoming large.

[0164] As a result, the leak current between respective N⁻ typeepitaxial layers 3 a, 3 b and 3 c is extremely small so that theelements, such as transistors, formed in each N⁻ type epitaxial layer 3a to 3 c can be sufficiently electrically isolated.

[0165] Furthermore, according to this manufacturing method, a CMPpolishing process is carried out, in particular, on polysilicon film 10so that the top surface of buried polysilicon films 10 a and 10 b andthe surface of thermal oxide film 9 are located in approximately thesame plane. Thereby, the flatness of the subsequently formed thermaloxide film or of the interlayer insulating film in the portions abovetrenches 6 a and 6 b is greatly increased so as to make it possible tocarry out a microscopic process.

[0166] Embodiment 5

[0167] A manufacturing method for a semiconductor device according toEmbodiment 5 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, the steps up to the step shown in FIG. 34 are the same as thoseshown in FIGS. 1 to 5 described in Embodiment 1.

[0168] Next, as shown in FIG. 35, a CMP polishing process is carried outon polysilicon film 10. At this time, the CMP polishing process iscarried out to such a degree that a thin polysilicon film 10 remains onthermal oxide film 9. It is preferable for the film thickness of thisremaining polysilicon film 10 to be 50 nm, or less.

[0169] Next, as shown in FIG. 36, a thermal oxide film 63, of which thefilm thickness is approximately 0.6 μm, is formed by carrying out athermal oxidation process under the condition wherein polysilicon film10 remains on thermal oxide film 9. After that, the same steps as thosefrom the step shown in FIG. 8 to the step shown in FIG. 15 described inEmbodiment 1 are followed so as to complete an NPN transistor T, asshown in FIG. 37.

[0170] According to the above described manufacturing method for asemiconductor device, polishing is completed under the condition whereinpolysilicon film 10 remains on thermal oxide film 9 in the step shown inFIG. 35 and, then, thermal oxide film 63 is formed through thermaloxidation. Thereby, the portions of thermal oxide films 9 a and 9 blocated on the sidewalls in the vicinity of the edges of the openings oftrenches 6 a and 6 b are prevented from becoming thick at the time ofthe formation of thermal oxide film 63.

[0171] Predetermined etching is carried out on this thermal oxide film63 to the required minimum amount in a step similar to the step shown inFIG. 9 described in Embodiment 1 and, after that, a thermal oxidationprocess is carried out.

[0172] Thereby, recesses 64 a to 64 d that occur in the portions ofthermal oxide film 61 located on the sidewalls in the vicinity of theedges of the openings of trenches 6 a and 6 b become comparatively smallso that the film thickness of the portions of thermal oxide films 9 aand 9 b located on the sidewalls in the vicinity of the edges of theopenings of trenches 6 a and 6 b can be prevented from becoming great.

[0173] As a result, the leak current between respective N⁻ typeepitaxial layers 3 a, 3 b and 3 c is extremely small so that theelements, such as transistors, formed in each N⁻ type epitaxial layer 3a to 3 c can be sufficiently electrically isolated.

[0174] In addition, as described in Embodiment 4, a CMP polishingprocess is carried out on polysilicon film 10 so that the top surface ofpolysilicon film 10 is located in approximately the same plane. Thereby,flatness of the subsequently formed thermal oxide film or of theinterlayer insulating film in the portions above trenches 6 a and 6 b isgreatly increased so as to make it possible to carry out a microscopicprocess.

[0175] Embodiment 6

[0176] A manufacturing method for a semiconductor device according toEmbodiment 6 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, the steps up to the step shown in FIG. 38 are the same as thosefrom the step shown in FIG. 1 to the step shown in FIG. 3 described inEmbodiment 1.

[0177] Next, as shown in FIG. 39, a silicon nitride film 71 is formedaccording to a CVD method. It is preferable for the film thickness ofthis silicon nitride film 71 to be approximately 50 nm, or less. This isbecause, in the case that the film thickness of silicon nitride film 71becomes great, stress due to silicon nitride film 71 affects N⁻ typeepitaxial layers 3 a to 3 c so that the leak current prevention effectis reduced.

[0178] Next, as shown in FIG. 40, silicon nitride films 71 a to 71 d aremade to remain only on the sidewalls of trenches 6 a and 6 b by carryingout etching on the entire surface of silicon nitride film 71 inaccordance with reactive anisotropic etching (RIE).

[0179] Next, thermal oxide films 5 a to 5 c and 4 a to 4 c are used as amask so that boron is implanted into P⁻ type silicon substrate 1 throughthermal oxide films 7 a and 7 b and, thereby, channel cut layers 8 a and8 b are formed as shown in FIG. 41. After that, thermal oxide films 5 ato 5 c, 4 a to 4 c, 7 a and 7 b are removed through wet etching andthermal oxide films 9 a to 9 d, of which the film thickness isapproximately 0.1 μm, are formed by carrying out a thermal oxidationprocess.

[0180] Next, as shown in FIG. 42, a polysilicon film 10, of which thefilm thickness is approximately 2 μm, is formed. Next, as shown in FIG.43, etching is carried out on the entire surface of polysilicon film 10and, thereby, buried polysilicon films 10 a and 10 b are formed so thatthe polysilicon films remain only within trenches 6 a and 6 b.

[0181] Next, as shown in FIG. 44, thermal oxide film 9 is made thickerby carrying out a thermal oxidation process so that a thermal oxide film31, of which the film thickness is approximately 0.6 μm, is formed. Thisthermal oxide film 31 corresponds to thermal oxide film 112 according tothe prior art.

[0182] After that, the same steps as those from the step shown in FIG. 8to the step shown in FIG. 10 described in Embodiment 1 are followed soas to gain the structure shown in FIG. 45. That is to say, after theformation of a collector lead-out layer 14 and a base lead-out layer 16by means of a gas diffusion method, thermal oxide film 31 is removedthrough etching of the entire surface of the oxide film to the requiredminimum amount and, then, a thermal oxide film 33, of which the filmthickness is approximately 0.1 μm, is formed in accordance with athermal oxidation process.

[0183] After that, the same steps as those from the step shown in FIG.11 to the step shown in FIG. 15 described in Embodiment 1 are followedso as to complete an NPN transistor T, as shown in FIG. 46.

[0184] According to the above described manufacturing method for asemiconductor device, silicon nitride films 71 a to 71 d, which have theability to prevent oxidation, are formed by allowing thermal oxide films7 a to 7 d to intervene between the sidewalls of trenches 6 a and 6 band the silicon nitride films. In addition, etching is not carried outat all on thermal oxide film 9 located on N⁻ type epitaxial layers 3 ato 3 c.

[0185] Thereby, in the step shown in FIG. 43, recesses 111 a to 111 d,as shown in FIG. 63, are prevented from being created along thesidewalls in the vicinity of edges of the openings of trench portions 6a and 6 b. Then, silicon nitride films 71 a to 71 d are formed asoxidation prevention films between buried polysilicon films 10 a, 10 band thermal oxide film 7 and, thereby, the portions of thick oxide films7 a and 7 b located on the sidewalls in the vicinity of the edges of theopenings of trenches 6 a and 6 b are, in particular, prevented frombeing oxidized during the thermal treatment at the time of the formationof thermal oxide film 31 so that the film thickness of these portionscan be prevented without fail from becoming greater in comparison withthe case of Embodiment 1.

[0186] As a result, the leak current between N⁻ type epitaxial layers 3a to 3 c is further reduced so that the elements, such as transistors,formed in each N⁻ type epitaxial layer 3 a to 3 c can be electricallyisolated from each other without fail.

[0187] Embodiment 7

[0188] A manufacturing method for a semiconductor device according toEmbodiment 7 of the present invention and a semiconductor device gainedin accordance with this manufacturing method are herein described.First, the steps up to the step shown in FIG. 47 are the same as thosefrom the step shown in FIG. 1 to the step shown in FIG. 2 described inEmbodiment 1. After that, wet etching of oxide films or a cleaningprocess is carried out in order to remove reaction products that areproduced at the time when trenches 6 a and 6 b are created.

[0189] After that, as shown in FIG. 48, a thermal oxidation process iscarried out and, thereby, sacrificial oxide films 7 a and 7 b, of whichthe film thickness is approximately 50 nm, are formed on the sidewallsof trenches 6 a and 6 b, and the like. Next, as shown in FIG. 49,silicon oxide films 5 a to 5 c and 4 a to 4 c are used as a mask so thatboron is implanted through thermal oxide films 7 a and 7 b and, thereby,channel cut layers 8 a and 8 b are formed in the portions of P typesilicon substrate 1.

[0190] Next, as shown in FIG. 50, sacrificial oxide films 7 a and 7 bare removed by carrying out etching. At this time, since the etching iscarried out on silicon oxide films 5 a to 5 c, the film thicknessthereof becomes thinner. Next, as shown in FIG. 51, a silicon nitridefilm 75 is formed by means of a CVD method. It is preferable for thefilm thickness of silicon nitride film 75 to be approximately 50 nm, orless, when taking into consideration the stress of the silicon nitridefilm itself.

[0191] Next, as shown in FIG. 52, anisotropic etching is carried out onsilicon nitride film 75 so that silicon nitride films 75 a to 75 d,respectively, remain only on the sidewalls of trenches 6 a and 6 b.Next, as shown in FIG. 53, silicon oxide films 5 a to 5 c and 4 a to 4 care removed by carrying out wet etching.

[0192] Next, as shown in FIG. 54, a thermal oxide film 9, of which thefilm thickness is approximately 0.1 μm, is formed by carrying out athermal oxidation process. After that, portions of thermal oxide film 9located at the bottoms of trenches 6 a and 6 b are removed so as toexpose portions of P⁻ type silicon substrate 1. Next, a polysilicon film10, of which the film thickness is approximately 2 μm, is formed onthermal oxide film 9.

[0193] At this time, polysilicon film 10 and the portions of P⁻ typesilicon substrate 1 contact each other at the bottoms of trenches 6 aand 6 b. In particular, in polysilicon film 10 in this embodiment, it isdesirable for boron, for example, to be added so as to make anelectrical connection with the portions of P⁻ type silicon substrate 1.

[0194] Next, as shown in FIG. 55, etching is carried out on the entiresurface of polysilicon film 10 and, thereby, buried polysilicon films 10a and 10 b are formed so that the polysilicon films remain only withintrenches 6 a and 6 b. At this time, etching is carried out onpolysilicon film 10 under the conditions wherein etching rates ofsilicon nitride films 75 a to 75 d and of polysilicon film 10 becomesubstantially the same etching rate and, thereby, the top surface ofburied polysilicon films 10 a and 10 b and the top surface of siliconnitride films 75 a to 75 d are located in approximately the same plane.

[0195] Next, as shown in FIG. 56, the film thickness of thermal oxidefilm 9 is increased by carrying out a thermal oxidation process so as toform a thermal oxide film 76, of which the film thickness isapproximately 0.6 μm. This thermal oxide film 76 corresponds to thermaloxide film 112 according to the conventional manufacturing method.

[0196] After that, the same steps as those from the step shown in FIG. 8to the step shown in FIG. 10 described Embodiment 1 are followed so asto gain the structure shown in FIG. 57. That is to say, after theformation of a collector lead-out layer 14 and of a base lead-out layer16 by means of a gas diffusion method, thermal oxide film 76 is removedthrough etching of the entire surface of the oxide film to the requiredminimum amount and, then, a thermal oxide film 78, of which the filmthickness is approximately 0.1 μm, is formed according to a thermaloxidation process.

[0197] After that, the same steps as those from the step shown in FIG.11 to the step shown in FIG. 15 described Embodiment 1 are followed soas to complete an NPN transistor T, as shown in FIG. 58. In particular,an isolation contact 26 d that is electrically connected P⁻ type siliconsubstrate 1 is formed in this semiconductor device.

[0198] According to the above described manufacturing method for asemiconductor device, the sidewalls of trenches 6 a and 6 b are,respectively, covered with silicon nitride films 75 a to 75 d that havethe ability to prevent oxidation. In addition, etching is not carriedout at all on thermal oxide film 9 located on N⁻ type epitaxial layers 3a to 3 c.

[0199] Thereby, in the step shown in FIG. 55, recesses 111 a to 111 d,as shown in FIG. 63, are not created along the sidewalls in the vicinityof the edges of the openings of trench portions 6 a and 6 b. Then,silicon nitride films 75 a to 75 b are formed as oxidation preventionfilms between buried polysilicon films 10 a, 10 b and thermal oxide film7 and, thereby, the portions of thermal oxide films 7 a and 7 b locatedalong the sidewalls in the vicinity of the edges of the openings oftrench portions 6 a and 6 b are prevented from being oxidized, inparticular, during a thermal treatment at the time of the formation ofthermal oxide film 76 so that the film thickness of these portions canbe prevented without fail from becoming greater in comparison with thecase in Embodiment 1.

[0200] As a result, the leak current between N⁻ type epitaxial layers 3a to 3 c is further reduced so that the elements, such as transistors,formed in each N⁻ type epitaxial layer 3 a to 3 c can be electricallyisolated from each other without fail.

[0201] Furthermore, in a semiconductor device gained according to thismanufacturing method, buried polysilicon film 10 b formed in trench 6 bis electrically connected to the portion of P type silicon substrate 1at the bottom of trench 6 b.

[0202] Thereby, the potential of isolation contact 26 d becomes the sameas the potential of P⁻ type silicon substrate 1 so that the potential P⁻type silicon substrate 1 can be secured via isolation contact 26 d.

[0203] In contrast to this, in an NPN transistor according to anisolation structure based on the conventional PN junction, P⁺ isolationdiffusion layers 80 a and 80 b are, respectively, formed in therespective spaces between epitaxial layers 3 a to 3 c for isolation asshown in FIG. 59.

[0204] Therefore, it is necessary to form contacts on P⁺ isolationdiffusion layers 80 a and 80 b so as to secure the potential byproviding aluminum electrodes on these portions in order to secure thepotential of P⁻ type silicon substrate 1. Furthermore, such P⁺ typeisolation diffusion layers need to be provided over the entirety of thesubstrate in order to secure the potential of P⁻ type silicon substrate1 with respect to the entirety of the semiconductor device.

[0205] In the present semiconductor device, the potential of P⁻ typesilicon substrate 1 can be directly secured via buried polysilicon film10 b formed in trenches 6 a and 6 b so that the semiconductor device caneasily be fixed at the potential of P⁻ type silicon substrate 1.

[0206] Here, though in each of the above described embodimentspolysilicon films are buried in the trenches, a semiconductor material,such as Si, Ge, or the like, may be used, in addition to the above, aslong as the material has a coefficient of thermal expansion close to thevalue of the coefficient of thermal expansion of a silicon substrate.

[0207] Here, in the above described manufacturing method for asemiconductor device described in each of the embodiments, an NPNtransistor is cited as an example of an element of the description. Thepresent invention can be applied not only to an NPN transistor but,also, to a PNP transistor. In addition, the present invention can beapplied to not only a bipolar transistor but, also, to a MOS transistor.Furthermore, it is clear that, the present invention can be applied tonot only a transistor but, also, to another element.

[0208] The embodiments disclosed herein should be considered asillustrative from all points of view and are not limitative. The presentinvention is not defined by the above description but, rather, isdefined by the claims and is intended to include the meanings equivalentto the claims as well as all of the modifications within the scope.

[0209] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate of a first conductive type having a mainsurface; a layer of a second conductive type formed on said main surfaceof said semiconductor substrate; a trench portion created so as topenetrate said layer of the second conductive type and so as to reach toa region in said semiconductor substrate for separating said layer ofthe second conductive type into one element formation region and anotherelement formation region; an insulating film formed on the sidewalls ofsaid trench; and a buried semiconductor region formed on said insulatingfilm so as to fill in said trench portion; wherein said insulating filmis formed from the bottom over to the edges of the opening of saidtrench portion having an approximately uniform film thickness so as notto give any stress to said layer of the second conductive type.
 2. Thesemiconductor device according to claim 1, wherein said insulating filmincludes a silicon oxide film.
 3. The semiconductor device according toclaim 2, wherein said insulating film includes an oxidation preventionfilm formed between said silicon oxide film and said buriedsemiconductor region.
 4. The semiconductor device according to claim 3,wherein said buried semiconductor region is electrically connected tothe region of said semiconductor substrate of the first conductive typeat the bottom of said trench portion.
 5. The semiconductor deviceaccording to claim 4, wherein said buried semiconductor region includesan impurity of the first conductive type.
 6. The semiconductor deviceaccording to claim 3, wherein said oxidation prevention film is asilicon nitride film.
 7. The semiconductor device according to claim 1,wherein said insulating film comprises an oxidation prevention film. 8.The semiconductor device according to claim 7, wherein said buriedsemiconductor region is electrically connected to the region of saidsemiconductor substrate of the first conductive type at the bottom ofsaid trench portion.
 9. The semiconductor device according to claim 8,wherein said buried semiconductor region includes an impurity of thefirst conductive type.
 10. The semiconductor device according to claim8, wherein said oxidation prevention film is a silicon nitride film. 11.The semiconductor device according to claim 1, wherein atop surface ofsaid layer of the second conductive type, an upper edge of saidinsulating film and a top surface of said buried semiconductor regionare in approximately the same plane.
 12. A manufacturing method for asemiconductor device, comprising the steps of: forming a layer of asecond conductive type on a main surface of a semiconductor substrate ofa first conductive type; creating a trench portion for separating saidlayer of the second conductive type into one element formation regionand another element formation region; forming a first insulating film onsaid layer of the second conductive type, including on its sidewall thatis exposed within said trench portion; forming a semiconductor film onsaid first insulating film so as to fill into said trench portion;forming a buried semiconductor region by allowing said semiconductorfilm to remain within said trench portion; and forming a secondinsulating film that is thicker than said first insulating film bycarrying out a thermal treatment on said first insulating film locatedon a top surface of said layer of the second conductive type.
 13. Themanufacturing method for a semiconductor device according to claim 12,after the formation of said second insulating film comprising the stepsof: carrying out a process on said second insulating film so as toexpose a surface of a region wherein at least a predetermined element isformed in said layer of the second conductive type; and forming a thirdinsulating film on said layer of the second conductive type so as tocover said exposed region of said layer of the second conductive type.14. The manufacturing method for a semiconductor device according toclaim 12, wherein a process is carried out on said semiconductor film sothat said semiconductor film remains on said first insulating film insaid step of forming a buried semiconductor region; and wherein saidthermal treatment is carried out on a portion including saidsemiconductor film that remains on said first insulating film in saidstep of forming a second insulating film.
 15. The manufacturing methodfor a semiconductor device according to claim 14, wherein said processof a semiconductor film is carried out through polishing in said step offorming a buried semiconductor region.
 16. The manufacturing method fora semiconductor device according to claim 12, wherein a process iscarried out on said semiconductor film so as to expose a surface of saidfirst insulating film, located on a top surface of said layer of thesecond conductive type, in said step of forming a buried semiconductorregion; and wherein said thermal treatment is carried out, under thecondition wherein a surface of said first insulating film is exposed, insaid step of forming a second insulating film.
 17. The manufacturingmethod for a semiconductor device according to claim 16, wherein saidprocess of a semiconductor film is carried out through polishing in saidstep of forming a buried semiconductor region.
 18. A manufacturingmethod for a semiconductor device, comprising the steps of: forming alayer of a second conductive type on a main surface of a semiconductorsubstrate of a first conductive type; creating a trench portion forseparating said layer of the second conductive type into one elementformation region and another element formation region; forming anoxidation prevention film on a sidewall exposed within said trenchportion; the step of forming a semiconductor film on said oxidationprevention film so as to fill into said trench portion; forming a buriedsemiconductor region by allowing said semiconductor film to remainwithin said trench portion; and forming an insulating film on the layerof the second conductive type by carrying out a thermal treatment. 19.The manufacturing method for a semiconductor device according to claim18, further comprising the step of exposing a region of saidsemiconductor substrate located at the bottom of said trench portionafter the formation of said oxidation prevention film and before theformation of said semiconductor film; wherein said semiconductor film iselectrically connected to the exposed region of said semiconductorsubstrate in said step of forming a semiconductor film.
 20. Themanufacturing method for a semiconductor device according to claim 18,wherein said oxidation prevention film includes a silicon nitride film.